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Data Sheet
UART INTERFACE
Table 10. Frames in the UART Packet
ADE7953
The ADE7953 provides a simple universal asynchronous
receiver/transmitter (UART) interface that allows all the functions
of the ADE7953 to be accessed using only two single-direction
pins. The UART interface allows an isolated communication
Frame
F1
F2
F3
Function
Read/write
Address MSB
Address LSB
interface to be achieved using only two low cost opto-isolators.
The UART interface operates at a fixed baud rate of 4800 bps
and is therefore suitable for low speed designs.
The UART interface on the ADE7953 is accessed via the Tx pin
(Pin 26), which transmits data from the ADE7953 , and the Rx
pin (Pin 27), which receives data from the microcontroller. A
simple master/slave topology is implemented on the UART inter-
face with the ADE7953acting as the slave. All communication
is initiated by the sending of a valid frame by the master (the
microcontroller) to the slave (the ADE7953 ). The format of the
frame is shown in Figure 72.
As shown in Figure 72, each frame consists of 10 bits. Each bit is
sent at a bit rate of 4800 bps, resulting in a frame time of 2.08 ms
((1/4800) × 10). A wait period of 6 ms should be added from
when the UART communication mode is established using the
CS and SCLK pins to when the first frame is sent. A minimum
wait of 0.2 ms should be included between frames. All frame
data is sent LSB first.
Communication via the UART interface is initiated by the
master sending a packet of three frames (see Table 10).
F1 determines whether the communication is a read or a write
operation, and the following two frames (F2 and F3) select the
register that is to be accessed. Each frame consists of eight data
bits, as shown in Figure 72. A read is issued by writing the value
0x35 to F1, and a write is issued by writing the value 0xCA to
F1. Any other value is interpreted as invalid and results in an
unsuccessful communication with the ADE7953 . The address
bytes are sent MSB first; therefore, F2 contains the most
significant portion of the address, and F3 contains the least
significant portion of the address. The bits within each address
frame are sent LSB first.
The ADE7953 UART interface uses two timeouts, t 1 and t 2 , to
synchronize the communication and to prevent the communi-
cation from halting. The first timeout, t 1 , is the frame-to-frame
delay and is fixed at 4 ms max. The second timeout, t 2 , is the
packet-to-packet delay and is fixed at 6 ms min. These two
timeouts act as a reset for the UART function. More informa-
tion about how the timeouts are implemented is provided in
the UART Read section and the UART Write section.
Verification of a successful UART communication can be
achieved by implementing a write/read/verify sequence in the
microcontroller. Successful communications are also recorded
in the LAST_ADD, LAST_RWDATA, and LAST_OP registers,
as described in the Communication Verification section.
t 2
SCLK
CS
t 1
Rx
FRAME
t 1 = FRAME DELAY: 0.2ms (MIN), 4ms (MAX)
t 2 = PACKET DELAY: 6ms (MIN)
Figure 72. UART Frame
Rev. B | Page 55 of 72
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